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| HT46R343 A/D Type 8-Bit OTP MCU with OPA and 88 LED Driver Technical Document * Tools Information * FAQs * Application Note - HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM - HA0075E MCU Reset and Oscillator Circuits Application Note - HA0114E Calibrating the OPA Input Voltage Offset on the HT46R32/322/34/342, HT45R32/34 and HT45RM03 Features * Operating voltage: * Up to 0.5ms instruction cycle with 8MHz system clock fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V * 37 bidirectional I/O lines (max.) * support 88 LED driver * Single interrupt input shared with an I/O line * Two 8-bit programmable timer/event counter with at VDD=5V * 6-level subroutine nesting * 16 channel 12-bit resolution A/D converter * Integrated single operational amplifier or comparator selectable via configuration option * Peripheral clock output - PCK * Dual 8-bit PWM outputs shared with I/O lines * Bit manipulation instruction * Full table read instruction * 63 powerful instructions * All instructions executed in one or two machine overflow interrupt * Integrated crystal and RC oscillator * Watchdog Timer * 409615 Program Memory capacity * 1928 Data Memory capacity * Integrated PFD function for sound generation * Power-down and wake-up functions reduce power cycles * Low voltage reset function * 44-pin QFP package consumption General Description The HT46R343 is 8-bit, high performance, RISC architecture microcontroller devices. With their fully integrated A/D converter they are especially suitable for applications which interface to analog signals, such as those from sensors. The addition of an internal operational amplifier/comparator and PWM modulation functions further adds to the analog capability of these devices. With the comprehensive features of low power consumption, I/O flexibility, programmable frequency divider, timer functions, oscillator options, multi-channel A/D Converter, OP/Comparator, Pulse Width Modulation function, LED driver, Power-down and wake-up functions etc, the application scope of these devices is broad and encompasses areas such as sensor signal processing, motor driving, industrial control, consumer products, subsystem controllers, etc. Rev. 1.00 1 October 11, 2007 HT46R343 Block Diagram TM R0C P D 6 /IN T TM R0 PFD0 In te rru p t C ir c u it STACK P ro g ra m ROM P ro g ra m C o u n te r IN T C TM R1C TM R1 PFD1 M M U P r e s c a le r X P D 5 /T M R 0 fS YS U X P r e s c a le r P A 4 /T M R 1 PA4 M U X fS YS fS YS /4 In s tr u c tio n R e g is te r MP M U X DATA M e m o ry W DT /4 W DT OSC PEC PE In s tr u c tio n D ecoder ALU T im in g G e n e ra to r S h ifte r PA3,PA5 PCC OSC2 OS RE VD VS S S D C1 ACC LVR PC MUX PW M PDC STATUS PD P o rt E PE0~PE7 P o rt D PD PD PD PD PD 0 /P 1 /P 2 /P 5 /T 6 /IN WM0 WM1 CK MR0 T P o rt C P C 0 /A N 8 ~ P C 7 /A N 1 5 1 6 -C h a n n e l A /D C o n v e rte r PBC APN APP APO L o w O ffs e t O P -a m p PAC PA P o rt A PA PA PA PA 0~ 3 /P 4 /T 5~ PA F M PA D 2 R1 7 PB P o rt B P B 0 /A N 0 ~ P B 7 /A N 7 Rev. 1.00 2 October 11, 2007 HT46R343 Pin Assignment PC PC PC PC 7 /A 6 /A 5 /A 4 /A PE PE PE PE PE PE PE N1 N1 N1 N1 2 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 3 4 5 7 6 5 4 3 2 1 PE PA PA PA PA PA PA PA PA 0 7 6 5 PC3 PC2 PC PC PB PB PB PB PB PB PB /A N /A N 1 /A 0 /A 7 /A 6 /A 5 /A 4 /A 3 /A 2 /A 1 /A 10 N9 N8 N7 N6 N5 N4 N3 N2 N1 11 33 32 31 30 H T46R 343 4 4 Q F P -A 29 28 27 26 25 24 23 OSC2 OSC1 0 1 2 4 /T R M 1 3 /P F D VDD RES PD0 PD1 PD2 PD5 PD6 VSS APP APN PB0 /A N 0 /A P O /P /P /P /T /IN WM0 WM1 CK MR0 T Pin Description Pin Name PA0~PA2 PA3/PFD PA4/TMR1 PA5~PA7 I/O Options Pull-high Wake-up PA3 or PFD Timer 0 or Timer 1 (PFD Clock Source) Description Bidirectional 8-bit input/output port. Each pin can be configured as wake-up input by configuration options. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pins on the port have pull-high resistors. The PFD and TMR1 pins are pin-shared with PA3 and PA4. PA0~PA7 can be used as LED driver (source end). 16 lines AD inut pun-shared with PB and PC. Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pins on the port have pull-high resistors. Pins PB, PC are pin-shared with the A/D input pins. The A/D inputs are selected via software instructions. Once selected as an A/D input, the I/O function and pull-high resistor are disabled automatically. About PB0/AN0/APO: If the pin is PB0 (setting by ADCS.PCR3~0=00), ADC and OP amp should be power off automatically. If the pin is AN0 (setting by ADCS.PCR3~0), APO is connected with AN0 pin together and OP amp on/off is controlled by OPAC.OPAEN. Bi-directional 4-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pins on this port have pull-high resistors. PD0/PD1 are pin-shared with the PWM0/PWM1 outputs selected via configuration option. PD0, PD1, PD2, PD5, PD6 are pin-shared with the PWM0, PWM1, PCK, TMR0, INT output selected via configuration option. Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. A configuration option determines if all pins on the port have pull-high resistors. PE0~PE7 can be used as LED driver (sink end). APN and APP are the internal operational amplifier, negative input pin and positive input pin respectively . Schmitt trigger reset input. Active low. Positive power supply Negative power supply, ground. I/O PB0/AN0/APO, PB1/AN1~ PB7/AN7, PC0/AN8~ PC7/AN15 I/O Pull-high PD0/PWM0 PD1/PWM1 PD2/PCK PD5/TMR0 PD6/INT I/O Pull-high PD0 or PWM0 PD1 or PWM1 PD2 or PCK PE0~PE7 I/O Pull-high APN APP RES VDD VSS I I I 3/4 3/4 3/4 3/4 3/4 3/4 Rev. 1.00 3 October 11, 2007 HT46R343 Pin Name OSC1 OSC2 I/O I O Options Crystal or RC Description OSC1, OSC2 are connected to an external RC network or external crystal, determined by configuration option, for the internal system clock. If the RC system clock option is selected, pin OSC2 can be used to measure the system clock at 1/4 frequency. Absolute Maximum Ratings Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ..............................................................150mA Total Power Dissipation .....................................500mW Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C IOH Total............................................................-100mA Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Symbol Parameter VDD VDD Operating Voltage Operating Current (Crystal OSC) Operating Current (RC OSC) Operating Current (Crystal OSC, RC OSC) Standby Current (WDT Enabled) Standby Current (WDT Disabled) Input Low Voltage for I/O Ports, TMR and INT Input High Voltage for I/O Ports, TMR and INT Input Low Voltage (RES) Input High Voltage (RES) Low Voltage Reset I/O Port Sink Current (PA, PB, PC, PD) I/O Port Source Current (PB, PC, PD, PE) PE Ports Sink Current for LED Driver 3/4 3/4 3V 5V 3V 5V 5V 3V 5V 3V 5V 3/4 3/4 3/4 3/4 3/4 3V 5V 3V 5V 3V 5V Operating Temperature: 40C~+85C, Ta=25C Test Conditions Min. Conditions fSYS=4MHz fSYS=8MHz No load, fSYS=4MHz ADC disable No load, fSYS=4MHz ADC disable No load, fSYS=8MHz ADC disable No load, system HALT No load, system HALT 3/4 3/4 3/4 3/4 3/4 VOL=0.1VDD VOL=0.1VDD VOH=0.9VDD VOH=0.9VDD VOL=0.1VDD VOL=0.1VDD 2.2 3.3 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 0.7VDD 0 0.9VDD 2.7 4 10 -2 -5 8 20 3/4 3/4 0.6 2 0.8 2.5 3 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3.0 8 20 -4 -10 16 40 5.5 5.5 1.5 4 1.5 4 5 5 10 1 2 0.3VDD VDD 0.4VDD VDD 3.3 3/4 3/4 3/4 3/4 3/4 3/4 V V mA mA mA mA mA mA mA mA mA V V V V V mA mA mA mA mA mA Typ. Max. Unit IDD1 IDD2 IDD3 ISTB1 ISTB2 VIL1 VIH1 VIL2 VIH2 VLVR IOL1 IOH1 IOL2 Rev. 1.00 4 October 11, 2007 HT46R343 Test Conditions Symbol Parameter VDD IOH2 PA Ports Source Current for LED Driver Pull-high Resistance 5V VAD IADC DNL INL A/D Input Voltage Additional Power Consumption if A/D Converter is Used ADC Differential Non-Linearity ADC Integral Non-Linearity 3/4 3V 5V 5V 5V 3/4 tAD=1ms tAD=1ms 3/4 3V 5V 3V Conditions VOH=0.9VDD VOH=0.9VDD 3/4 3/4 3/4 3/4 -4 -10 20 10 0 3/4 3/4 3/4 3/4 3/4 -8 -20 60 30 3/4 0.5 1.5 3/4 2.5 3/4 3/4 3/4 100 50 VDD 1 3 2 4 12 mA mA kW kW V mA mA mA mA Bits Min. Typ. Max. Unit RPH RESOLU Resolution A.C. Characteristics Test Conditions Symbol Parameter VDD fSYS System Clock (Crystal OSC, RC OSC) Timer I/P Frequency (TMR) Watchdog Oscillator Period 5V tWDT1 tWDT2 tRES tSST tLVR tINT tAD tADC tADCS Watchdog Time-out Period (WDT OSC) Watchdog Time-out Period (System Clock) External Reset Low Pulse Width System Start-up Timer Period Low Voltage Width to Reset Interrupt Pulse Width A/D Clock Period A/D Conversion Time A/D Sampling Time 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3V Conditions 2.2V~5.5V 3.3V~5.5V 2.2V~5.5V 3.3V~5.5V 3/4 3/4 3/4 3/4 3/4 Wake-up from HALT 3/4 3/4 3/4 3/4 3/4 400 400 0 0 45 32 215 217 1 3/4 0.25 1 1 3/4 3/4 3/4 3/4 3/4 3/4 90 65 3/4 3/4 3/4 1024 1 3/4 3/4 80 32 4000 8000 4000 8000 180 130 216 218 3/4 3/4 2 3/4 3/4 3/4 3/4 Min. Typ. Max. Ta=25C Unit kHz kHz kHz kHz ms ms tWDTOSC tSYS ms *tSYS ms ms ms tAD tAD fTIMER tWDTOSC Note: *tSYS=1/fSYS Rev. 1.00 5 October 11, 2007 HT46R343 OP Amplifier Electrical Characteristics Test Conditions Symbol Parameter VDD D.C. Electrical Characteristic VDD VOPOS1 VOPOS2 VCM PSRR CMRR tRES Operating Voltage Input Offset Voltage Input Offset Voltage Common Mode Voltage Range Power Supply Rejection Ratio Common Mode Rejection Ratio Response Time (Comparator) 3/4 5V 5V 3/4 3/4 5V 3/4 3/4 3/4 By Calibration 3/4 3/4 VCM=0~VDD-1.4V Input overdrive=10mV 3 -10 -2 VSS 60 60 3/4 3/4 3/4 3/4 3/4 80 80 3/4 5.5 10 2 VDD1.4V 3/4 3/4 2 V mV mV V dB dB ms Conditions Min. Typ. Max. Unit Ta=25C A.C. Electrical Characteristic VOPOS1 SR GBW Open Loop Gain Slew Rate +, Slew Rate Gain Band Width 3/4 3/4 3/4 No load RL=1M, CL=100p 3/4 60 3/4 3/4 80 0.1 3/4 3/4 3/4 100 dB V/ms kHz Rev. 1.00 6 October 11, 2007 HT46R343 Functional Description Execution Flow The system clock for the microcontroller is derived from either a crystal or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter controls the sequence in which the instructions stored in program memory are executed and whose contents specify full range of program memory. After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction. The lower byte of the program counter, PCL, is a readable and writeable register. Moving data into the PCL performs a short jump. The destination will be within 256 locations. When a control transfer takes place, an additional dummy cycle is required. S y s te m O S C 2 (R C C lo c k o n ly ) PC T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4 PC PC+1 PC+2 F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 ) F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C ) F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 ) Execution Flow Mode Initial Reset External Interrupt Timer/Event 0 Counter Overflow Timer/Event 1 Counter Overflow A/D Converter Interrupt Skip Loading PCL Jump, Call Branch Return from Subroutine Program Counter *11 0 0 0 0 0 *10 0 0 0 0 0 *9 0 0 0 0 0 *8 0 0 0 0 0 *7 0 0 0 0 0 *6 0 0 0 0 0 *5 0 0 0 0 0 *4 0 0 0 0 1 *3 0 0 1 1 0 *2 0 1 0 1 0 *1 0 0 0 0 0 *0 0 0 0 0 0 Program Counter+2 *11 #11 S11 *10 #10 S10 *9 #9 S9 *8 #8 S8 @7 #7 S7 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0 Program Counter Note: PC11~PC8: Current Program Counter bits #11~#0: Instruction Code bits S11~S0: Stack register bits @7~@0: PCL bits Rev. 1.00 7 October 11, 2007 HT46R343 Program Memory - ROM The program memory is used to store the program instructions which are to be executed as well as table data and interrupt entries. It is structured into 4K15 bits device, which can be addressed by both the program counter and table pointer. Certain locations in the program memory are reserved for use by the reset and by the interrupt vectors. * Location 000H This vector is reserved for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. * Location 004H the table, the location must be placed in TBLP. The TBLH register is read only and cannot be restored. If the main routine and the ISR, Interrupt Service Routine, both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. In such a case errors can occur. Therefore, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be used in both the main routine and the ISR, the interrupt is should be disabled prior to the table read instruction. It should not be re-enabled until the TBLH has been backed up. All table related instructions require two cycles to complete their operation. These areas may function as normal program memory depending upon requirements. 000H 0 0 40 H 0 0 48 H 00CH 010H D e v ic e In itia liz a tio n P r o g r a m E x te r n a l In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r 0 In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r 1 In te r r u p t S u b r o u tin e A /D C o n v e r te r In te r r u p t S u b r o u tin e P ro g ra m M e m o ry This vector is used by the external interrupt INT. If the external interrupt pin on the device receives a low going edge, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. * Location 008H This vector is used by the Timer/Event Counter 0. If a timer overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full. * Location 00CH This vector is used by the Timer/Event Counter 1. If a timer overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full. * Location 010H n00H nFFH L o o k - u p T a b le ( 2 5 6 w o r d s ) This vector is used by the A/D converter. When an A/D cycle conversion is complete, the program will jump to this location and begin execution if the A/D interrupt is enabled and the stack is not full. * Table location 700H 7FFH L o o k - u p T a b le ( 2 5 6 w o r d s ) 1 4 b its Program Memory Stack Register - STACK This is a special part of the memory which is used to save the contents of the program counter only. The stack is organized into 6 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer, known as stack pointer, and is also neither readable nor writeable. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, Table Location Any location in the Program Memory space can be used as a look-up table. The instructions TABRDC [m] (the current page, 1 page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH. Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, and the remaining bits are read as 0. The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register, which indicates the table location. Before accessing Instruction TABRDC [m] TABRDL [m] *11 P11 1 *10 P10 1 *9 P9 1 *8 P8 1 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0 Table Location Note: *11~*0: Table location bits @7~@0: Table pointer bits 8 P11~P8: Current program counter bits Rev. 1.00 October 11, 2007 HT46R343 RET or RETI, the program counter is restored to its previous value from the stack. After a device reset, the stack pointer will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. When the stack pointer is decremented, using a RET or RETI instruction, the interrupt will be serviced. This feature prevents a stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry will be lost. Only the most recent 6 return addresses are stored. Data Memory - RAM The data memory is divided into two functional groups: special function registers and general purpose data memory. The general purpose memory has a structure of 1928 bits. Most locations are read/write, but some are read only. The remaining space between the end of the Special Purpose Data Memory and the beginning of the General Purpose Data Memory is reserved for future expanded usage, reading these locations will obtain a result of 00H. The general purpose data memory, addressed from 40H to FFH, is used for user data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by the SET [m].i and CLR [m].i instructions. They are also indirectly accessible through memory pointer register, MP. Indirect Addressing Register Location 00H is an indirect addressing register that is not physically implemented. Any read/write operation on [00H] accesses data memory pointed to by the MP register. Reading location 00H itself indirectly will return the result 00H. Writing indirectly results in no operation. The memory pointer register, MP, is a 8-bit register. Accumulator The accumulator is closely related to ALU operations and can carry out immediate data operations. Any data movement between two data memory locations must pass through the accumulator. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions: * Arithmetic operations - ADD, ADC, SUB, SBC, DAA * Logic operations - AND, OR, XOR, CPL * Rotation - RL, RR, RLC, RRC * Increment and Decrement - INC, DEC * Branch decision - SZ, SNZ, SIZ, SDZ .... The ALU not only saves the results of a data operation but also changes the status register. 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 39H 40H TM R1 TM R1C PA PAC PB PBC PC PCC PD PDC PE PEE PW M0 PW M1 IN T C 1 OPAC ADRL ADRH ADCR ACSR :U nused R e a d a s "0 0 " G e n e ra l P u rp o s e D a ta M e m o ry (1 9 2 B y te s ) S p e c ia l P u r p o s e D a ta M e m o ry TM R0 TM R0C STATUS IN T C 0 ACC PCL TBLP TBLH In d ir e c t A d d r e s s in g R e g is te r MP FFH RAM Mapping Rev. 1.00 9 October 11, 2007 HT46R343 Status Register - STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition operations related to the status register may give different results from those intended. The TO flag can be affected only by system power-up, a WDT time-out or executing the CLR WDT or HALT instruction. The PDF flag can be affected only by executing the HALT or CLR WDT instruction or a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. Interrupt The devices provide an external interrupt, an internal timer/event counter interrupt and an A/D converter interrupt. The Interrupt Control Register, INTC, contains the interrupt control bits to set the enable or disable and the interrupt request flags. Once an interrupt subroutine is serviced, all the other interrupts will be blocked by clearing the EMI bit. This scheme may prevent any further interrupt nesting. Other interrupt requests may happen during this interval but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit in INTC0/INTC1 may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. Function C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation, otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction, otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero, otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa, otherwise OV is cleared. PDF is cleared by a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status (0AH) Register Bit No. 0 1 2 3 4 5 6 7 Label EMI EEI ET0I ET1I EIF T0F T1F 3/4 Function Controls the master (global) interrupt (1=enabled; 0=disabled) Controls the external interrupt (1=enabled; 0=disabled) Controls the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled) Controls the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled) External interrupt request flag (1=active; 0=inactive) Internal Timer/Event Counter 0 request flag (1=active; 0=inactive) Internal Timer/Event Counter 1 request flag (1=active; 0=inactive) Unused bit, read as 0 INTC (0BH) Register Rev. 1.00 10 October 11, 2007 Bit No. 0 Label C 1 2 3 4 5 6, 7 AC Z OV PDF TO 3/4 HT46R343 Bit No. 0 1~3 4 5~7 Label EADI 3/4 ADF 3/4 Function Control the A/D converter interrupt (1=enabled; 0=disabled) Unused bit, read as 0 A/D converter request flag (1=active; 0=inactive) Unused bit, read as 0 INTC1 (1EH) Register All interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at a specified location in the program memory. Only the program counter is pushed onto the stack. If the contents of the register or status register are altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. External interrupts are triggered by a high to low transition on the INT pin, which will set the related interrupt request flag, EIF, which is bit 4 of INTC0. When the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag, EIF, and EMI bits will be cleared to disable other interrupts. The internal timer/event counter 0 interrupt is initialised by setting the timer/event counter interrupt request flag, T0F, which is bit 5 of INTC0, caused by a timer overflow. When the interrupt is enabled, the stack is not full and the T0F bit is set, a subroutine call to location 008H will occur. The related interrupt request flag, T0F, will be reset and the EMI bit cleared to disable further interrupts. The internal timer/event counter 1 interrupt is initialised by setting the timer/event counter interrupt request flag, T1F, which is bit 6 of INTC1, caused by a timer overflow. When the interrupt is enabled, the stack is not full and the T1F bit is set, a subroutine call to location 00CH will occur. The related interrupt request flag, T1F, will be reset and the EMI bit cleared to disable further interrupts. The A/D converter interrupt is initialised by setting the A/D converter request flag, ADF, which is bit 4 of INTC1, caused by an end of A/D conversion. When the interrupt is enabled, the stack is not full and the ADF bit is set, a subroutine call to location 010H will occur. The related interrupt request flag, ADF, will be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1. Of course, the stack must not be full. To return from the interrupt subroutine, a RET or RETI instruction may be executed. A RETI instruction will set the EMI bit to enable an interrupt service, but a RET instruction will not. Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Interrupt Source External Interrupt Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow A/D Converter Interrupt Priority 1 2 3 4 Vector 004H 008H 00CH 010H Once the interrupt request flags, T0F/T1F, EIF, ADF, are set, they will remain in the INTC0/INTC1 register until the interrupts are serviced or cleared by a software instruction. It is recommended that a program does not use the CALL subroutine within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged once the CALL operates in the interrupt subroutine. Oscillator Configuration There are two oscillator circuits in the microcontroller, namely an RC oscillator and a crystal oscillator, the choice of which is determined by a configuration option. When the system enters the Power-down mode the system oscillator stops and ignores external signals to conserve power. If an RC oscillator is used, an external resistor between OSC1 and VSS is required whose resistance value must range from 24kW to 1MW. The system clock, divided by 4, can be monitored on pin OSC2 if a pull-high resistor is connected. This signal can be used to synchronise external logic. The RC oscillator provides the most cost effective solution, however the frequency of V OSC1 DD 470pF OSC1 OSC2 C r y s ta l O s c illa to r fS YS /4 RC OSC2 O s c illa to r System Oscillator 11 October 11, 2007 Rev. 1.00 HT46R343 oscillation may vary with VDD, temperature and the process variations. It is, therefore, not suitable for timing sensitive operations where an accurate oscillator frequency is desired. If the Crystal oscillator is used, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator; no other external components are required. Instead of a crystal, a resonator can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required, If the oscillating frequency is less than 1MHz. The WDT oscillator is a free running on-chip RC oscillator, and requires no external components. Even if the system enters the power down mode, the system clock is stopped, but the WDT oscillator keeps running with a period of approximately 65ms at 5V. The WDT oscillator can be disabled by a configuration option to conserve power. Watchdog Timer - WDT The WDT clock source comes from either its own integrated RC oscillator, known as the WDT oscillator, or the instruction clock, which is the system clock divided by 4. The choice of which one is used is decided by a configuration option. This timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by a configuration option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation. Once the internal WDT oscillator (RC oscillator with a period of 65ms at 5V nominal) is selected, it is divided by 32768~65536 to get a time-out period of approximately 2.1s~4.3s. This time-out period may vary with temperatures, VDD and process variations. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operate in the same manner except that in the Power-down state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by external logic. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT instruction will stop the system clock. The WDT overflow under normal operation will initialise a chip reset and set the status bit TO. But in the S y s te m C lo c k /4 O p tio n S e le c t W DT OSC fS 8 - b it C o u n te r 7 - b it C o u n te r T T W D T T im e - o u t 15 16 fS /2 ~ fS /2 CLR W DT Power-down mode, the overflow will initialisze a warm reset, and only the program counter and SP are reset to zero. To clear the contents of the WDT, three methods are adopted; external reset (a low level on the RES pin), a software instruction and a HALT instruction. The software instruction include CLR WDT and the other set - CLR WDT1 and CLR WDT2. Of these two types of instruction, only one can be active depending on the configuration option - CLR WDT times selection option. If the CLR WDT is selected (i.e. CLR WDT times equal one), any execution of the CLR WDT instruction will clear the WDT. In the case that CLR WDT1 and CLR WDT2 are chosen (i.e. CLR WDT times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip as a result of time-out. Power Down Operation - HALT The HALT mode is initialised by the HALT instruction and results in the following... * The system oscillator will be turned off but the WDT oscillator keeps running (if the WDT oscillator is selected). * The contents of the on chip Data Memory and regis- ters remain unchanged. * WDT will be cleared and start counting again (if the WDT clock is from the WDT oscillator). * All of the I/O ports maintain their original status. * The PDF flag is set and the TO flag is cleared. The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialisation and the WDT overflow performs a warm reset. After the TO and PDF flags are examined, the reason for the chip reset can be determined. The PDF flag is cleared by a system power-up or executing the CLR WDT instruction and is set when executing the HALT instruction. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the program counter and Stack Pointer; the others keep their original status. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by the options. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it is awakening from an interrupt, two Watchdog Timer Rev. 1.00 12 October 11, 2007 HT46R343 sequences may happen. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the HALT mode, the wake-up function of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period will be inserted after wake-up. If the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. To minimise power consumption, all the I/O pins should be carefully managed before entering the status. Reset There are three ways in which a reset can occur: * RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation The functional unit chip reset status are shown below. Program Counter Interrupt WDT 000H Disable Clear. After master reset, WDT begins counting Timer/Event Counter Off Input/Output Ports Stack Pointer Input mode Points to the top of the stack VDD RES S S T T im e - o u t C h ip R eset tS ST Reset Timing Chart V DD V DD The WDT time-out during HALT is different from other chip reset conditions, since it can perform a warm re set that resets only the program counter and stack pointer, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers are reset to the initial condition when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different chip resets. TO 0 u 0 1 1 PDF 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT 0 .0 1 m F 100kW RES 0 .1 m F 100kW RES 10kW 0 .1 m F B a s ic Reset C ir c u it H i-n o is e Reset C ir c u it Reset Circuit Note: Most applications can use the Basic Reset Circuit as shown, however for applications with extensive noise, it is recommended to use the Hi-noise Reset Circuit. Note: u means unchanged To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RES reset) or the system awakes from the HALT state. When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will enable the SST delay. An extra option load time delay is added during system reset (power-up, WDT time-out at normal mode or RES reset). HALT W DT RES W a rm R eset OSC1 SST 1 0 - b it R ip p le C o u n te r S y s te m R eset C o ld R eset Reset Configuration Rev. 1.00 13 October 11, 2007 HT46R343 The registers states are summarised in the following table. Register MP ACC PCL TBLP TBLH STATUS INTC0 TMR0 TMR0C TMR1 TMR1C PA PAC PB PBC PC PCC PD PDC PE PEC PWM0 PWM1 INTC1 OPAC ADRL ADRH ADCR ACSR Note: Reset (Power On) xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx --xx xxxx --00 xxxx -000 0000 xxxx xxxx 00-0 1000 xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 -11- -111 -11- -111 1111 1111 1111 1111 xxxx xxxx xxxx xxxx ---0 ---0 0000 1000 xxxx ---xxxx xxxx 0100 0000 1-00 --00 * stands for warm reset u stands for unchanged x stands for unknown WDT Time-out (Normal Operation) uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu --1u uuuu -000 0000 xxxx xxxx 00-0 1000 xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 -11- -111 -11- -111 1111 1111 1111 1111 xxxx xxxx xxxx xxxx ---0 ---0 0000 1000 xxxx ---xxxx xxxx 0100 0000 1-00 --00 RES Reset (Normal Operation) uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu --uu uuuu -000 0000 xxxx xxxx 00-0 1000 xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 -11- -111 -11- -111 1111 1111 1111 1111 xxxx xxxx xxxx xxxx ---0 ---0 0000 1000 xxxx ---xxxx xxxx 0100 0000 1-00 --00 RES Reset (HALT) uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu --01 uuuu -000 0000 xxxx xxxx 00-0 1000 xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 -11- -111 -11- -111 1111 1111 1111 1111 xxxx xxxx xxxx xxxx ---0 ---0 0000 1000 xxxx ---xxxx xxxx 0100 0000 1-00 --00 WDT Times-out (HALT)* uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu --11 uuuu -uuu uuuu uuuu uuuu uu-u uuuu uuuu uuuu uu-u u--uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uu- -uuu -uu- -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---u ---u uuuu uuuu uuuu ---uuuu uuuu uuuu uuuu u-uu --uu Rev. 1.00 14 October 11, 2007 HT46R343 Timer/Event Counter Two timer/event counter (TMR) are implemented in the microcontroller. The timer/event counter contains an 8-bit programmable count-up counter and the clock may come from external source or an internal clock source. An internal clock source comes from fsys (fSYS/4). Using an external clock input allows the user to count external events, measure time internals or pulse widths, or generate an accurate time base. While using the internal clock allows the user to generate an accurate time base. There are two registers related to the Timer/Event Counter; TMR0 (TMR1), TMR0C (TMR1C). Writing TMR0 (TMR1) will transfer the specified data to Timer/Event Counter registers. Reading the TMR0 (TMR1) will read the contents of the Timer/Event Counter. The TMRC0 (TMR1C) is a control register, which defines the operating mode, counting enable or disable and an active edge. The T0TM0 & T0TM1 (T1TM0 & T1TM1) bits define the operation mode. The event count mode is used to count external events, which means that the clock source is from an external TMR0 (TMR1) pin. The timer mode functions as a normal timer with the clock source coming from the internal selected clock source. Finally, the pulse width measurement mode can be used to count the high or low-level duration of the external signal TMR0 (TMR1), and the counting is based on the internal selected clock source. In the event count or timer mode, the timer/event counter starts counting at the current contents in the timer/event counter and ends at FFH. Once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request flag T0F (T1F). In the pulse width measurement mode with the values of the T0ON & T0E ( T1ON &T1E) equal to 1, after the TMR0(TMR1) has received a transient from low to high (or high to low if the T0E(T1E) bit is 0), it will start counting until the TMR0(TMR1) returns to the original level and resets the T0ON(T1ON). The measured result remains in the timer/event counter even if the activated transient occurs again. In other words, only 1-cycle measurement can be made until the T0ON (T1ON) is set. The cycle measurement will re-function as long as it receives further transient pulse. In this operation mode, the timer/event counter begins counting not according to the logic level but to the transient edges. In the case of counter overflow, the counter is reloaded from the timer/event counter register and issues an interrupt request, as in the other two modes, i.e., event and timer modes. To enable the counting operation, the Timer ON bit T0ON (T1ON) should be set to 1. In the pulse width measurement mode, the T0ON (T1ON) is automatically cleared after the measurement cycle is completed. But in the other two modes, the T0ON (T1ON) can only be reset by instructions. The overflow of the Timer/Event Counter is one of the wake-up sources and can also be applied to a PFD (Programmable Frequency Divider) Function Defines the prescaler stages, PSC2, PSC1, PSC0= 000: fINT=fSYS 001: fINT=fSYS/2 010: fINT=fSYS/4 011: fINT=fSYS/8 100: fINT=fSYS/16 101: fINT=fSYS/32 110: fINT=fSYS/64 111: fINT=fSYS/128 Defines the TMR active edge of the timer/event counter: In Event Counter Mode (T0M1,T0M0)=(0,1): 1:count on falling edge; 0:count on rising edge In Pulse Width measurement mode (T0M1,T0M0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge Enable or disable the timer counting (0=disable; 1=enable) Unused bits, read as 0 Defines the operating mode (T0M1, T0M0)= 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR0C (0EH) Register Bit No. Label 0 1 2 T0PSC0 T0PSC1 T0PSC2 3 T0E 4 5 T0ON 3/4 T0M0 T0M1 6 7 Rev. 1.00 15 October 11, 2007 HT46R343 Bit No. 0~2 Label 3/4 Unused bits, read as 0 Defines the TMR active edge of the timer/event counter: In Event Counter Mode (T1M1,T1M0)=(0,1): 1:count on falling edge; 0:count on rising edge In Pulse Width measurement mode (T1M1,T1M0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge Enable or disable the timer counting (0=disable; 1=enable) Unused bits, read as 0 Defines the operating mode (T1M1, T1M0)= 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR1C (11H) Register Function 3 T1E 4 5 T1ON 3/4 T1M0 T1M1 6 7 PW M (6 + 2 ) C o m p a re fS YS T o P D 0 /P D 1 C ir c u it 8 - s ta g e P r e s c a le r 8 -1 M U X PSC2~PSC0 TM R0 T0E T0M 1 T0M 0 T0O N P u ls e W id th M e a s u re m e n t M o d e C o n tro l 8 - B it T im e r /E v e n t C o u n te r 0 1 /2 O v e r flo w to In te rru p t PFD0 f IN T D a ta B u s T0M 1 T0M 0 8 - B it T im e r /E v e n t C o u n te r P r e lo a d R e g is te r R e lo a d Timer/Event Counter 0 fS YS /4 TM R1 T1E T1M 1 T1M 0 T1O N D a ta B u s T1M 1 T1M 0 8 - B it T im e r /E v e n t C o u n te r P r e lo a d R e g is te r R e lo a d P u ls e W id th M e a s u re m e n t M o d e C o n tro l 8 - B it T im e r /E v e n t C o u n te r 1 1 /2 O v e r flo w to In te rru p t PFD1 Timer/Event Counter 1 Rev. 1.00 16 October 11, 2007 HT46R343 output by options. When the PFD function is selected, executing SET [PA].3 instruction to enable PFD output and executing CLR [PA].3 instruction to disable PFD output. In the case of a timer/event counter OFF condition, writing data to the timer/event counter preload register will also reload that data to the timer/event counter. But if the timer/event counter is turned on, data written to it will only be kept in the timer/event counter preload register. The timer/event counter will still operate until an overflow occurs. When the timer/event counter TMR0 (TMR1) is read, the clock is blocked to avoid errors, as this may results in a counting error. Blocking of the clock issue should be taken into account by the programmer. It is strongly recommended to load a desired value into the TMR0 (TMR1) register first, before turning on the related timer/event counter, for proper operation since the initial value of TMR0 (TMR1) is unknown. Due to the timer/event scheme, the programmer should pay special attention on the instruction to enable then disable the timer for the first time, whenever there is a need to use the timer/event function, to avoid unpredictable result. After this procedure, the timer/event function can be operated normally. The definitions are as shown. The overflow signal of timer/event 0/1 counter can be used to generate the PFD signal. The timer prescaler is also used as the PWM counter. Input/Output Ports There are 37 bidirectional input/output lines in the microcontroller, labeled as PA, PB, PC, PD and PE, which are mapped to the data memory of [12H], [14H], [16H], [18H] and [1AH] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H, 16H, 18H or 1AH). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC, PCC, PDC, PEC) to control the input/output configuration. With this control register, CMOS output or Schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically (i.e. on-the-fly) under software control. To function as an input, the corresponding latch of the control register must write 1. The input source also depends on the control register. If the control register bit is 1, the input will read the pad state. If the control register bit is 0, the contents of the latches will move to the internal bus. The latter is possible in the read-modify-write instruction. After a device reset, the input/output lines will default to inputs and remain at a high level or floating state, dependent upon the pull-high configuration options. Each bit of these input/output latches can be set or cleared by the SET [m].i and CLR [m].i (m=12H, 14H, 16H, 18H or 1AH) instructions. V C o n tr o l B it D a ta B u s D CK S Q W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r Q P u ll- H ig h O p tio n DD D a ta B it D Q CK S Q M U X PFDEN (P A 3 ) U X W a k e - u p o p tio n W r ite D a ta R e g is te r PA0 PA3 PA4 PA5 PB0 PC0 PD0 PD1 PD2 PD5 PD6 PE0 ~PA2 /P F D /T M R 1 ~PA7 /A N 0 ~ P B 7 /A N 7 /A N 8 ~ P C 7 /A N 1 5 /P W M 0 /P W M 1 /P C K /T M R 0 /IN T ~PE7 (P D 0 o r P W M ) PA3 PFD M R e a d D a ta R e g is te r S y s te m W a k e - u p ( P A o n ly ) IN T fo r P D 6 O n ly T M R 0 fo r P D 5 O n ly T M R 1 fo r P A 4 O n ly Input/Output Ports Rev. 1.00 17 October 11, 2007 HT46R343 Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. Each I/O line has a pull-high option. Once the pull-high configuration option is selected, the I/O line has a pull-high resistor, otherwise, theres none. Take note that a non-pull-high I/O line operating in input mode will cause a floating state. Pin PA3 is pin-shared with the PFD signal. If the PFD configuration option is selected, the output signal in the output mode for PA3 will be the PFD signal generated by the timer/event counter overflow signal. The input mode always retains its original functions. Once the PFD option is selected, the PFD output signal is controlled by the PA3 data register only. Writing a 1 to the PA3 data register will enable the PFD output function and writing 0 will force the PA3 to remain at 0. The I/O functions for PA3 are shown below. I/O Mode PA3 Note: I/P O/P (Normal) (Normal) Logical Input Logical Output I/P (PFD) Logical Input O/P (PFD) PFD (Timer on) two PWM functions shared with pins PD0 and PD1. If the PWM functions are enabled, the PWM signals will appear on PD0 and PD1, the pins are setup as outputs. Writing a 1 to the PD0 or PD1 data register will enable the PWM outputs to function while writing a 0 will force the PD0 and PD1 outputs to remain at 0. The I/O functions of PD0 and PD1 are as shown. I/O Mode PD0 PD1 I/P O/P (Normal) (Normal) Logical Input Logical Output I/P (PWM) Logical Input O/P (PWM) PWM0 PWM1 It is recommended that unused I/O lines should be setup as output pins by software instructions to avoid consuming power under input floating states. PWM The microcontroller provides a 2 channel (6+2) bits PWM0/PWM1 output shared with PD0/PD1. The PWM channel has its data register denoted as PWM0 and PWM1. The frequency source of the PWM counter comes from fSYS. The PWM register is an eight bit register. Once PD0/PD1 are selected as PWM outputs and the output function of PD0/PD1 is enabled (PDC.0=0 or PDC.1=0), writing a 1 to the PD0/PD1 data register will enable the PWM output function while writing a 0 will force the PD0/PD1 outputs to stay at 0. A PWM cycle is divided into four modulation cycles (modulation cycle 0~modulation cycle 3). Each modulation cycle has 64 PWM input clock period. In a (6+2) bit PWM function, the contents of the PWM register is divided into two groups. Group 1 of the PWM register is denoted by DC which is the value of PWM.7~PWM.2. Group 2 is denoted by AC which is the value of PWM.1~PWM.0. The PFD frequency is the timer/event counter overflow frequency divided by 2. Pins PD6, PD5 and PA4 are pin-shared with INT, TMR0 and TMR1 pins respectively. The PB and PC can also be used as A/D converter inputs. The A/D function will be described later. There are fS YS /2 [P W M ] = 1 0 0 PW M [P W M ] = 1 0 1 PW M [P W M ] = 1 0 2 PW M [P W M ] = 1 0 3 PW M PW M 2 6 /6 4 m o d u la tio n p e r io d : 6 4 /fS M o d u la tio n c y c le 0 YS 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4 2 6 /6 4 2 6 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4 2 6 /6 4 M o d u la tio n c y c le 1 PW M 2 6 /6 4 M o d u la tio n c y c le 2 c y c le : 2 5 6 /fS YS 2 5 /6 4 M o d u la tio n c y c le 3 2 6 /6 4 M o d u la tio n c y c le 0 6+2 PWM Mode Rev. 1.00 18 October 11, 2007 HT46R343 In a PWM cycle, the duty cycle of each modulation cycle is shown in the table. Parameter AC (0~3) i PA0~PA7 PE0~PE7 H T -M C U L E D D is p la y 8 x 8 A rra y Peripheral Clock Output - PCK The device also provides a Peripheral Clock Output (PCK) which is pin-shared with PD2. Once the PD2 is selected as the PCK outputs and the output function of PD2 is enabled (PDC.2 =0), writing 1 to PA0 data register will enable the PCK output function and writing 0 will force the PD2 to stay at 0. The PCK clock frequency can be optional : fSYS/16 or fSYS/32 ( by configuration option). PCK output = 500kHz or 250kHz if fSYS=8MHz. Recommend to clear PD2 before entering HALT mode. PD2 CK M U fS YS /4 fP P C K D iv id e r P C K C lo c k X P D 2 /P C K P C K D iv id e r R a tio O p tio n ( 4 o r 8 ) P C K O p tio n A/D Converter The 16 channel 12-bit resolution A/D converter is implemented in the microcontrollers. The reference voltage for the A/D is VDD. The A/D converter contains 4 special registers, which are; ADRL, ADRH, ADCR and ACSR. Rev. 1.00 19 October 11, 2007 HT46R343 Register ADRL ADRH Note: Bit7 D3 D11 Bit6 D2 D10 Bit5 D1 D9 Bit4 D0 D8 Bit3 3/4 D7 Bit2 3/4 D6 Bit1 3/4 D5 Bit0 3/4 D4 D0~D11 is A/D conversion result data bit LSB~MSB. ADRL (20H), ADRH (21H) Register Bit No. 0 1 2 3 4 5 6 7 Label ACS0 ACS1 ACS2 PCR0 PCR1 PCR2 EOCB Function ACS3[ACSR], ACS2, ACS1, ACS0: selected A/D channel Port B, C configuration selection. If PCR0, PCR1, PCR2 and PCR3[ACSR] are all zero, the ADC circuit is power off to reduce power consumption Indicates end of A/D conversion. (0 = end of A/D conversion) Each time bits 3~5 change state the A/D should be initialised by issuing a START signal, otherwise the EOCB flag may have an undefined condition. See Important note for A/D initialisation. START Starts the A/D conversion. (0(R)1(R)0= start; 0(R)1= Reset A/D converter and set EOCB to 1) ADCR (22H) Register ACS3, ACS2, ACS1, ACS0 0000 0001 0010 0011 0100 0101 0110 0111 Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ACS3, ACS2, ACS1, ACS0 1000 1001 1010 1011 1100 1101 1110 1111 A/D Channel Channel AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 Bit No. Label Select the A/D converter clock source. 0, 0: fSYS/2 ADCS0 0, 1: fSYS/8 ADCS1 1, 0: fSYS/32 1, 1: Undefined 3/4 ACS3 PCR3 3/4 TEST Unused bit, read as 0. Bit3 of 4bit A/D channel selection Function 0 1 2~3 4 5 6 7 Bit3 of 4bit Port B, C configuration selection. Unused bit, read as 0. For internal test only. ACSR (23H) Register Rev. 1.00 20 October 11, 2007 HT46R343 PCR3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 PCR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PCR1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PCR0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 15 PC7 PC7 PC7 PC7 PC7 PC7 PC7 PC7 PC7 PC7 PC7 PC7 PC7 PC7 PC7 14 PC6 PC6 PC6 PC6 PC6 PC6 PC6 PC6 PC6 PC6 PC6 PC6 PC6 PC6 13 PC5 PC5 PC5 PC5 PC5 PC5 PC5 PC5 PC5 PC5 PC5 PC5 PC5 12 PC4 PC4 PC4 PC4 PC4 PC4 PC4 PC4 PC4 PC4 PC4 PC4 11 PC3 PC3 PC3 PC3 PC3 PC3 PC3 PC3 PC3 PC3 PC3 10 PC2 PC2 PC2 PC2 PC2 PC2 PC2 PC2 PC2 PC2 AN10 9 PC1 PC1 PC1 PC1 PC1 PC1 PC1 PC1 PC1 AN9 AN9 AN9 AN9 AN9 AN9 AN9 8 PC0 PC0 PC0 PC0 PC0 PC0 PC0 PC0 AN8 AN8 AN8 AN8 AN8 AN8 AN8 AN8 7 PB7 PB7 PB7 PB7 PB7 PB7 PB7 AN7 AN7 AN7 AN7 AN7 AN7 AN7 AN7 AN7 6 PB6 PB6 PB6 PB6 PB6 PB6 PB6 AN6 AN6 AN6 AN6 AN6 AN6 AN6 AN6 AN6 5 PB5 PB5 PB5 PB5 PB5 PB5 AN5 AN5 AN5 AN5 AN5 AN5 AN5 AN5 AN5 AN5 4 PB4 PB4 PB4 PB4 PB4 AN4 AN4 AN4 AN4 AN4 AN4 AN4 AN4 AN4 AN4 AN4 3 PB3 PB3 PB3 PB3 AN3 AN3 AN3 AN3 AN3 AN3 AN3 AN3 AN3 AN3 AN3 AN3 2 PB2 PB2 PB2 AN2 AN2 AN2 AN2 AN2 AN2 AN2 AN2 AN2 AN2 AN2 AN2 AN2 1 PB1 PB1 AN1 AN1 AN1 AN1 AN1 AN1 AN1 AN1 AN1 AN1 AN1 AN1 AN1 AN1 0 PB0 AN0 AN0 AN0 AN0 AN0 AN0 AN0 AN0 AN0 AN0 AN0 AN0 AN0 AN0 AN0 AN11 AN10 AN12 AN11 AN10 AN13 AN12 AN11 AN10 AN14 AN13 AN12 AN11 AN10 AN15 AN14 AN13 AN12 AN11 AN10 Port B, C configuration M in im u m START o n e in s tr u c tio n c y c le n e e d e d , M a x im u m te n in s tr u c tio n c y c le s a llo w e d EOCB PC R2~ PCR0 A /D tA 000B DCS s a m p lin g tim e A /D tA DCS s a m p lin g tim e A /D s a m p lin g tim e tA D C S 101B 000B 1 . P B p o rt s e tu p a s I/O s 2 . A /D c o n v e r te r is p o w e r e d o ff to r e d u c e p o w e r c o n s u m p tio n 100B 100B AC S2~ ACS0 000B P o w e r-o n R eset R e s e t A /D c o n v e rte r 1 : D e fin e P B c o n fig u r a tio n 2 : S e le c t a n a lo g c h a n n e l A /D N o te : A /D c lo c k m u s t b e fS tA D C S = 3 2 tA D tA D C = 8 0 tA D YS 010B S ta rt o f A /D c o n v e r s io n 000B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n 001B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n d o n 't c a r e E n d o f A /D c o n v e r s io n tA D C c o n v e r s io n tim e tA D C c o n v e r s io n tim e YS tA D C A /D c o n v e r s io n tim e A /D /2 , fS /8 o r fS YS /3 2 A/D Conversion Timing Rev. 1.00 21 October 11, 2007 HT46R343 The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using EOCB Polling Method to detect end of conversion clr EADI ; disable ADC interrupt mov a,00000001B mov ACSR,a ; setup the ACSR register to select fSYS/8 as the A/D clock mov a,00100000B ; setup ADCR register to configure Port PB0~PB3 as A/D inputs mov ADCR,a ; and select AN0 to be connected to the A/D converter : : ; As the Port B channel bits have changed the following START ; signal (0-1-0) must be issued within 10 instruction cycles : Start_conversion: clr START set START ; reset A/D clr START ; start A/D Polling_EOC: sz EOCB ; poll the ADCR register EOCB bit to detect end of A/D conversion jmp polling_EOC ; continue polling mov a,ADRH ; read conversion result high byte value from the ADRH register mov adrh_buffer,a ; save result to user defined memory mov a,ADRL ; read conversion result low byte value from the ADRL register mov adrl_buffer,a ; save result to user defined memory : : jmp start_conversion ; start next A/D conversion Example: using interrupt method to detect end of conversion clr EADI ; disable ADC interrupt mov a,00000001B mov ACSR,a ; setup the ACSR register to select fSYS/8 as the A/D clock mov mov a,00100000B ADCR,a : ; setup ADCR register to configure Port PB0~PB3 as A/D inputs ; and select AN0 to be connected to the A/D converter ; As the Port B channel bits have changed the following START ; signal (0-1-0) must be issued within 10 instruction cycles : Start_conversion: clr START set START clr START clr ADF set EADI set EMI : : : ; ADC interrupt service routine ADC_ISR: mov acc_stack,a mov a,STATUS mov status_stack,a : : mov a,ADRH mov adrh_buffer,a mov a,ADRL mov adrl_buffer,a clr START set START clr START : : EXIT_INT_ISR: mov a,status_stack mov STATUS,a mov a,acc_stack reti Rev. 1.00 ; reset A/D ; start A/D ; clear ADC interrupt request flag ; enable ADC interrupt ; enable global interrupt ; save ACC to user defined memory ; save STATUS to user defined memory ; read conversion result high byte value from the ADRH register ; save result to user defined register ; read conversion result low byte value from the ADRL register ; save result to user defined register ; reset A/D ; start A/D ; restore STATUS from user defined memory ; restore ACC from user defined memory 22 October 11, 2007 HT46R343 Low Voltage Reset - LVR The microcontroller provides a low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~VLVR, such as what happens when changing a battery, the LVR will automatically reset the device internally. The LVR includes the following specifications: * The low voltage (0.9V~VLVR) has to remain in its origi- The relationship between VDD and VLVR is shown below. VDD 5 .5 V V OPR 5 .5 V V 3 .0 V 2 .2 V LVR nal state to exceed tLVR. If the low voltage state does not exceed tLVR, the LVR will ignore it and will not perform a reset function. * The LVR uses the OR function with the external RES 0 .9 V Note: signal to perform a chip reset. V 5 .5 V DD VOPR is the voltage range for proper chip operation at 4MHz system clock. V LVR LVR D e te c t V o lta g e 0 .9 V 0V R e s e t S ig n a l R eset *1 N o r m a l O p e r a tio n *2 R eset Low Voltage Reset Note: *1: To make sure that the system oscillator has stabilised, the SST provides an extra delay of 1024 system clock pulses before beginning normal operation. *2: Since the low voltage has to maintain in its original state and exceed tLVR, therefore tLVR delay enter the reset mode. OP Amplifier/Comparator The devices include an integrated operational amplifier or comparator, selectable via configuration option. The default is function is comparator. The input voltage offset is adjustable by using a common mode input to calibrate the offset value. APN VR APP APO The calibration process is as follows: APN APP S1 S2 APO S3 * Set bit AOFM=1 to select the offset cancellation mode - this closes switch S3 * Set the ARS bit to select which input pin is the reference voltage - closes either switch S1 or S2 * Adjust bits AOF0~AOF3 until the output status OPAOP has changed. * Set AOFM=0 to select the normal operating mode Rev. 1.00 23 October 11, 2007 HT46R343 Bit No. 0 1 2 3 4 Label AOF0 AOF1 AOF2 AOF3 ARS Function OP amp/comparator input offset voltage cancellation control bits OP amp/comparator input offset voltage cancellation reference selection bit 1/0 : select OPP/OPN (CP/CN) as the reference input Input offset voltage cancellation mode and OP amp/comparator mode selection 1: input offset voltage cancellation mode 0: OP amp/comparator OP amp/comparator output; positive logic OP amp/comparator enable/disable (1/0) If OP/comparator is disabled, output is floating. OPAC (1FH) Register 5 6 7 AOFM OPAOP OPAEN If the OP amp/comparator is disabled, the power consumption will be very small. To ensure that power consumption is minimised when the device is in the Power-down mode, the OP amp/comparator should be switched off by clearing bit OPAEN to 0 before entering the Power-down mode. Configuration Options The following table shows the various microcontroller configuration options. All of the configuration options must be properly defined to ensure correct system functioning. No. 1 2 3 4 5 6 7 8 9 10 WDT clock source: WDTOSC or T1 (fSYS/4) WDT function: enable or disable CLRWDT instruction(s): one or two clear WDT instruction(s) System oscillator: RC or crystal Pull-high resistors (PA, PB, PD): none or pull-high PWM enable or disable PA0~PA7 wake-up: enable or disable PFD enable or disable Low voltage reset selection: enable or disable LVR function. Comparator or OP selection Options Rev. 1.00 24 October 11, 2007 HT46R343 Application Circuits V DD VDD Reset C ir c u it RES 0 .1 m F VSS 100kW 0 .1 m F PA0~PA2 P A 3 /P F D P A 4 /T M R 1 PA5~PA7 V P B 0 /A N 0 ~ P B 7 /A N 7 P C 0 /A N 8 ~ P C 7 /A N 1 5 P D 0 /P W M P D 1 /P W M P D 2 /P C P D 5 /T M R P D 6 /IN K T 0 APN APP P B 0 /A N 0 A P O HT46R343 0 1 C1 R DD 470pF OSC OSC1 fS YS R C S y s te m O s c illa to r 24kW OSC2 OSC1 C r y s ta l/R e s o n a to r S y s te m O s c illa to r F o r R 1 , C 1 , C 2 s e e n o te OSC C ir c u it OSC1 OSC2 PE0~PE7 C2 R1 OSC2 O S C C ir c u it Note: 1. Crystal/resonator system oscillators For crystal oscillators, C1 and C2 are only required for some crystal frequencies to ensure oscillation. For resonator applications C1 and C2 are normally required for oscillation to occur. For most applications it is not necessary to add R1. However if the LVR function is disabled, and if it is required to stop the oscillator when VDD falls below its operating range, it is recommended that R1 is added. The values of C1 and C2 should be selected in consultation with the crystal/resonator manufacturer specifications. 2. Reset circuit The reset circuit resistance and capacitance values should be chosen to ensure that VDD is stable and remains within its operating voltage range before the RES pin reaches a high level. Ensure that the length of the wiring connected to the RES pin is kept as short as possible, to avoid noise interference. 3. For applications where noise may interfere with the reset circuit and for details on the oscillator external components, refer to Application Note HA0075E for more information. Rev. 1.00 25 October 11, 2007 HT46R343 Instruction Set Introduction C e n t ra l t o t he s u c c e s s f u l oper a t i on o f a n y microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be CLR PCL or MOV PCL, A. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Logical and Rotate Operations The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. Rev. 1.00 26 October 11, 2007 HT46R343 Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the SET [m].i or CLR [m].i instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] INCA [m] INC [m] DECA [m] DEC [m] Description Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory Cycles 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 1 1Note 1 1Note Flag Affected Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Logic Operation Increment & Decrement Rev. 1.00 27 October 11, 2007 HT46R343 Mnemonic Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Description Cycles Flag Affected 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 28 October 11, 2007 HT46R343 Instruction Definition ADC A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) ADD A,[m] Description Operation Affected flag(s) ADD A,x Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) AND A,[m] Description Operation Affected flag(s) AND A,x Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Rev. 1.00 Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ACC + [m] + C OV, Z, AC, C Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. ACC ACC + [m] OV, Z, AC, C Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ACC + x OV, Z, AC, C Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ACC + [m] OV, Z, AC, C Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND [m] Z Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ACC AND [m] Z 29 October 11, 2007 HT46R343 CALL addr Description Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack Program Counter + 1 Program Counter addr None Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] 00H None Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i 0 None Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF Operation Affected flag(s) CLR [m] Description Operation Affected flag(s) CLR [m].i Description Operation Affected flag(s) CLR WDT Description Operation Affected flag(s) CLR WDT1 Description Operation Affected flag(s) CLR WDT2 Description Operation Affected flag(s) Rev. 1.00 30 October 11, 2007 HT46R343 CPL [m] Description Operation Affected flag(s) CPLA [m] Description Complement Data Memory Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] [m] Z Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC [m] Z Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ACC + 00H or [m] ACC + 06H or [m] ACC + 60H or [m] ACC + 66H C Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] [m] - 1 Z Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] - 1 Z Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO 0 PDF 1 TO, PDF Operation Affected flag(s) DAA [m] Description Operation Affected flag(s) DEC [m] Description Operation Affected flag(s) DECA [m] Description Operation Affected flag(s) HALT Description Operation Affected flag(s) Rev. 1.00 31 October 11, 2007 HT46R343 INC [m] Description Operation Affected flag(s) INCA [m] Description Operation Affected flag(s) JMP addr Description Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] [m] + 1 Z Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] + 1 Z Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter addr None Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC [m] None Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC x None Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ACC None No operation No operation is performed. Execution continues with the next instruction. No operation None Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR [m] Z Operation Affected flag(s) MOV A,[m] Description Operation Affected flag(s) MOV A,x Description Operation Affected flag(s) MOV [m],A Description Operation Affected flag(s) NOP Description Operation Affected flag(s) OR A,[m] Description Operation Affected flag(s) Rev. 1.00 32 October 11, 2007 HT46R343 OR A,x Description Operation Affected flag(s) ORM A,[m] Description Operation Affected flag(s) RET Description Operation Affected flag(s) RET A,x Description Operation Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR x Z Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ACC OR [m] Z Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter Stack None Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter Stack ACC x None Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter Stack EMI 1 None Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 None Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 [m].7 None Affected flag(s) RETI Description Operation Affected flag(s) RL [m] Description Operation Affected flag(s) RLA [m] Description Operation Affected flag(s) Rev. 1.00 33 October 11, 2007 HT46R343 RLC [m] Description Operation Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 C C [m].7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 C C [m].7 C Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 None Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 C C [m].0 C Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 C C [m].0 C Affected flag(s) RLCA [m] Description Operation Affected flag(s) RR [m] Description Operation Affected flag(s) RRA [m] Description Operation Affected flag(s) RRC [m] Description Operation Affected flag(s) RRCA [m] Description Operation Affected flag(s) Rev. 1.00 34 October 11, 2007 HT46R343 SBC A,[m] Description Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] - C OV, Z, AC, C Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] - C OV, Z, AC, C Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] - 1 Skip if [m] = 0 None Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC [m] - 1 Skip if ACC = 0 None Set Data Memory Each bit of the specified Data Memory is set to 1. [m] FFH None Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i 1 None Operation Affected flag(s) SBCM A,[m] Description Operation Affected flag(s) SDZ [m] Description Operation Affected flag(s) SDZA [m] Description Operation Affected flag(s) SET [m] Description Operation Affected flag(s) SET [m].i Description Operation Affected flag(s) Rev. 1.00 35 October 11, 2007 HT46R343 SIZ [m] Description Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] + 1 Skip if [m] = 0 None Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] + 1 Skip if ACC = 0 None Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] OV, Z, AC, C Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] OV, Z, AC, C Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - x OV, Z, AC, C Operation Affected flag(s) SIZA [m] Description Operation Affected flag(s) SNZ [m].i Description Operation Affected flag(s) SUB A,[m] Description Operation Affected flag(s) SUBM A,[m] Description Operation Affected flag(s) SUB A,x Description Operation Affected flag(s) Rev. 1.00 36 October 11, 2007 HT46R343 SWAP [m] Description Operation Affected flag(s) SWAPA [m] Description Operation Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 [m].7 ~ [m].4 None Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3 ~ ACC.0 [m].7 ~ [m].4 ACC.7 ~ ACC.4 [m].3 ~ [m].0 None Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m] = 0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] Skip if [m] = 0 None Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i = 0 None Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None Affected flag(s) SZ [m] Description Operation Affected flag(s) SZA [m] Description Operation Affected flag(s) SZ [m].i Description Operation Affected flag(s) TABRDC [m] Description Operation Affected flag(s) TABRDL [m] Description Operation Affected flag(s) Rev. 1.00 37 October 11, 2007 HT46R343 XOR A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) XOR A,x Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ACC XOR [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR x Z Rev. 1.00 38 October 11, 2007 HT46R343 Package Information 44-pin QFP (1010) Outline Dimensions C D G 23 I 34 22 L F A B E 44 12 K 1 11 a J 33 H Symbol A B C D E F G H I J K L a Dimensions in mm Min. 13 9.9 13 9.9 3/4 3/4 1.9 3/4 0.25 0.73 0.1 3/4 0 Nom. 3/4 3/4 3/4 3/4 0.8 0.3 3/4 3/4 3/4 3/4 3/4 0.1 3/4 Max. 13.4 10.1 13.4 10.1 3/4 3/4 2.2 2.7 0.5 0.93 0.2 3/4 7 Rev. 1.00 39 October 11, 2007 HT46R343 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 86-21-6485-5560 Fax: 86-21-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 86-28-6653-6590 Fax: 86-28-6653-6591 Holmate Semiconductor, Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holmate.com Copyright O 2007 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 40 October 11, 2007 |
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